The invention relates to compensating a characteristic (a slew rate, for example) of a circuit.
Referring to FIG. 1, an integrated circuit package, or chip 5, might have a bias generator 6 for generating bias voltages for circuits 8 (e.g., I/O predrivers) of the chip 5. These bias voltages typically are transmitted from the bias generator 6 to the circuits 8 via bias distribution networks 7 (e.g., conductive traces and filtering capacitors).
Quite often, this global biasing scheme is used to adjust, or compensate, one or more characteristics (e.g., a slew rate or output resistance) of each circuit 8. One or more external bias resistors 4 might be used to set the desired value that is used to compensate the circuits 8 to different levels.
There may be some difficulties associated with these schemes. For example, the above-described global biasing scheme often encounters difficulties due to variations in the local climates among the circuits 8 (i.e., variations in the conditions, such as actual process parameters, temperatures, and voltages that define the local environments of the circuits 8). Also, the global biasing scheme may be subject to noise errors. Thus, these existing compensation schemes may somehow be less effective than desired. Also, the programming resistors have a tolerance (approximately 5%) which introduce compensation errors. Multiple resistors may be required. These resistors typically require package pins, on-chip pads and compensation generator circuitry, all which consume area.
Alternatively, a chip 10 (see FIG. 2) might use a local biasing scheme to compensate the circuits 8 in the neighboring area. In this scheme, each circuit 8 has its own bias generator 9 which furnishes bias voltages for compensation. The levels of the bias voltages may be adjusted via one or more resistors 11 that are coupled to each bias generator 9. As a result, each circuit 8 may be compensated independently of the other circuits 8. In this case, each circuit will be in its local environment.
Quite often, even with the local biasing scheme, it is difficult to adjust the level of the bias voltages to the desired levels due to tolerances of the resistors 11. Furthermore, the resistors 11 may introduce system noise which introduces additional jitters in the compensation setting.
Thus, there is a continuing need for a globally effective compensation circuit that accounts for local variability, without excessive noise induced errors, and is economical on package pins, on chip pads and provides a very accurate standard reference for compensation calibration.